ML Compute IP Engineer, Hardware/Software Integration/Validation

Key Skills

Algorithms, C++, Computer Vision (CV), Machine learning techniques, RTL design

Job Description

Minimum qualifications:

• Master's degree in Electrical, Computer Engineering, Computer Science, or equivalent practical experience.
• 5 years of experience in a architecture, hardware, or software co-design role.
• 2 years of experience in C/C++ development, working with Architectural Simulators, Performance Models, and benchmarking performance.
• Experience in co-design, architecture definition for ML, Computer Vision IPs, and accelerators.

Preferred qualifications:

• PhD in Electrical/Computer Engineering, Computer Science, or related field.
• 3 years of experience working on Silicon/Production hardware environments.
• 2 years of experience working with RTL Simulation or Emulation/FPGA technologies.
• Experience writing/debugging verilog/RTL code for ASIC/FPGA designs and waveform, including knowledge of chip design flows.
• Experience developing architectures for Machine Learning Accelerators and excellent debugging skills.
• Fundamentals in 2 of the following areas: computer architecture, compilers, computer arithmetic, ML algorithms, ASIC design.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Be part of the TPU team that builds Machine Learning Accelerator ASICs for Google and positively impact Google’s products and users of Google across the globe.

In this role you will be working on ASIC development, verification, software, tools and methodologies, and push the boundaries of chip-development and hardware/software co-design.

You will contribute to and manage cross-functional work streams focused on end-to-end hardware and software co-design to left-shift TPU software and system functionality and performance. You'll help the Chip team accomplish key criteria, meet chip and system schedules, and achieve readiness for production in various Silicon/System Validation environments. You will also serve as a key bridge between Architecture and Design teams and Compiler and Performance teams with technical depth and breadth across the machine learning compute IP.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $172,000-$263,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Perform performance analysis on ML workloads (both pre-Si and post-Si), contribute to compiler optimizations, and next-chip architecture definition.
• Manage architecture and chip spec reviews, develop the integration plan with Software and System partners, coordinate hardware and software delivery, and benchmark performance. Enable bring up of the ML Compute features through Compiler stack and ML workloads.
• Plan and design validation tests and micro-benchmarks to validate Chip functionality and performance. Develop detailed test plans, based on design specifications and coordination with a cross-functional team (e.g., design, DV, firmware, compiler, Architecture).
• Create hardware and software co-simulation methodologies leveraging RTL simulation, emulation, and FPGA environments as appropriate. Leverage simulators and models as required to correlate performance.
• Drive debug discussions with Design/DV/Software/Architecture teams and help root-cause functional failures and performance issues.