ASIC RTL Design Engineer, ML Accelerators, University Graduate

Key Skills

Agile methodologies, Machine learning techniques, Perl Programming, Python Programming, RTL design

Job Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.
• Experience with a scripting language (e.g., Perl or Python).

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent practical experience.
• Coursework in Digital Design, Computer Architecture, Digital Circuit Design, VLSI Design, Design-for-Test and/or Design Verification.
• Experience with IP development.
• Familiarity with Design Tools related to Verilog simulation, synthesis, static timing analysis, formal verification, power analysis, and/or place and route.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a key member of the team, you manage projects in multiple areas with your expertise. You also monitor the performance of vendors working on projects and evaluate new technologies.

We architect the system, design the chip logic, verify functional correctness, design the packaging, analyze power and thermal characteristics, and implement the physical design of silicon chips and IP. You will work closely with product groups around the company to deliver silicon solutions and systems that differentiate our products and provide a better user experience. To deliver on our mission, we create and improve design automation flows and infrastructure for chip design. Our work to accelerate workloads and communications becomes more important to enable the growing success of Google’s products.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $108,000-$158,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Contribute to the microarchitecture and RTL coding of blocks, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Develop SystemVerilog RTL to implement logic for ASIC/SoC products.
• Develop novel ways to automate generation of complex RTL designs.
• Contribute to design methodology, libraries, and code review.