ASIC RTL Design Engineer, Machine Learning

Key Skills

Java Programming, Design, Python Programming, SQL, Machine learning techniques, GPUs, Data Architecture

Job Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
• 2 years of experience with Application Specific Intergrated Circuit (ASIC) Design and/or Integration
• Experience in Verilog/System Verilog

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or a related field
• Knowledge of power/performance/area trade-offs
• Knowledge of accelerators (e.g., Machine Learning or GPUs) or similar high performance designs
• Understanding in computer architecture/memory subsystem architecture

About the job

As an ASIC RTL Design Engineer, you will interface with architects to align on features and interface with physical design teams to ensure efficient implementation to produce high-quality Power Performance Area (PPA). You will engage with cross-functional teams to integrate third-party IPs such as CPU cores and fabrics. You will work with Production and Silicon Validation teams to support chip bring-up and production test.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Architect, design, and verify digital logic using Verilog and SystemVerilog.
• Provide input on synthesis, timing closure, and physical design of digital blocks.
• Engage with system architects and sub-system owners to define specifications and chip functions.
• Perform power, area, and performance trade-off analyses of digital designs and architectures.
• Apply engineering best practices (e.g., code review, testing, and refactoring) to the design and implementation of ASIC blocks.