PMTS AI Silicon Design Engineer

Key Skills

Aartificial intelligence, Design, Effective communication skills, GPUs, Optimization, Planning and organization, RTL design, SoC integration

Job Description

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of AMD’s AIE Accelerators for client, server, and adaptable silicon devices. The ideal candidate will have proven experience in coding optimized RTL with custom and semi-custom cells to deliver industry leading performance/area and performance/power. In this role the candidate will work with Architecture team, design team to implement next generation AI accelerators. 

You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AI.

THE PERSON:

The ideal candidate should have demonstrated experience in the logic and digital design and development of processors (CPU, GPU, NPU, AI accelerators). The candidate must be able to communicate effectively and work optimally with different teams across AMD. 

KEY RESPONSIBILITIES:

• Define and specify micro-architecture of AI Engine building blocks based on architecture and PPA targets.
• Analyze design metrics and make implementation choices to optimize PPA
• Develop optimized ALU, Multiplier blocks to achieve best power, performance, and area.
• RTL design and debug of complex blocks in Verilog / System Verilog
• Work with verification and physical design teams to achieve high quality design and successful tape out

 PREFERRED EXPERIENCE:

• Outstanding foundation in SoC micro-architecture, and design with expertise in one or more of the following: CPU or GPU, Memory sub-system, Neural Network Processors.
• Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at logic design, and circuit levels
• ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes
• Strong verbal and written communication skills
• Ability to organize and present complex technical information
• Adept at collaboration among top-thinkers and architects with strong interpersonal skills to work across teams in different geographies

 ACADEMIC CREDENTIALS:

• BSEE or equivalent and 10 years of relevant work experience, or MSEE or equivalent with 8 years of experience

LOCATION: San Jose CA