Display Defect Metrology Engineer, Raxium

Key Skills

Data Analysis, Machine learning techniques, Python Programming

Job Description

Minimum qualifications:

• Master's degree in Electrical Engineering, Materials Science, Physics, or a related field, or equivalent practical experience.
• 5 years of experience working with semiconductor wafer defect metrology tools.
• 1 year of experience in machine learning models to accelerate automatic defect classification.

Preferred qualifications:

• Experience and expertise in image-based defect detection, classification, and machine learning algorithms.
• Knowledge of failure analysis (FA) techniques and ability to interpret and understand the defect origin leading to reduction and elimination path.
• Proficiency in Python programming and statistical analysis tools.
• Ability to learn fast, work independently, and adapt in a fast-paced, changing environment, preferably in manufacturing or production settings.
• Ability to communicate cross-functionally effectively (e.g., in-person, emails, reports, technical documents) with excellent investigative, critical thinking, and problem-solving skills.

About the job

As a Display Defect Metrology Engineer, you will play a pivotal role in driving advancements in inline wafer-level defect detection through the development and implementation of state-of-the-art metrology techniques. You will provide technical expertise and strategic direction to the metrology team, fostering a culture of innovation and continuous improvement. This role requires a high level of collaboration with process, integration, yield and device groups and a keen problem-solving mindset. This role is fully onsite in Fremont, CA and in wafer fabrication cleanroom environments.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $142,000-$211,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Guide development and implementation of advanced inline wafer defect metrology equipment and techniques for detection, classification, and analysis, utilizing cutting-edge inspection tools and data analysis.
• Develop and execute experiments to identify and characterize defect sources and formation mechanisms, proactively addressing potential yield issues through data-driven analysis.
• Collaborate with and drive equipment vendors to improve and optimize defect metrology tools and applications based on development requirements, ensuring optimal performance.
• Establish and maintain appropriate control charts, sampling plans, calibration, and measurement system analysis (MSA) including Gage R&R (GRR) for effective defect monitoring and process control, ensuring data integrity and process stability.
• Direct problem resolution processes for quality excursions, utilizing data analytics, methodical problem-solving, failure analysis, design of experiment (DOE), and mistake-proofing, while also documenting techniques, training personnel, and continuously improving metrology procedures to minimize cycle time impact.