SOC STA Engineer

Key Skills

Apache Hadoop, C Programming, C++, Data science techniques, Java Programming, Machine learning techniques, MapReduce, Python Programming, PyTorch, R Programming, Scala Programming, SQL, TensorFlow

Job Description

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. We are looking for an entry-level Static Timing Analysis (STA) professional who will help with the design, analysis, and implementation of timing fixes on system-on-chip (SOC) designs to ensure successful delivery to end client.

Job Responsibilities:

• Develop and own the SOC design requirements and specification.
• Architect/improve STA methodology/flow by working closely with technology process team, technology modeling team, CAD tools team, design execution team, and management team.
• Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages).
• Analyze, debug, and implement fixes for reported timing violations (setup, hold, slew, and capacitance) using defined STA CAD tools/flow.
• Collaborate with global CAD teams on design flow fixes and feature improvements.

Requirements:

Minimum Qualifications:

• Typically requires a bachelor’s degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts.
• Knowledge and over three years of experience in STA practices and concepts, such as timing sign-off, timing takedown, noise-induced events, Miller-capacitance, etc.
• Knowledge and over three years of experience in STA flow and CAD tools, such as Synopsys Primetime, Cadence Tempus, and experience in using them in an beginning-to-end project setting in a recent semiconductor technology nodes – 5nm/7nm/10nm and 14nm/16nm are preferred but 28nm/32nm acceptable.
• Excellent English communication skill in verbal and written.
• Able to work effectively with global team and be self-motivated to solve problems and manage deliverables.

Preferred Qualifications:

• Thorough understanding of Linux/Unix/BSD Internals, with experience working on Multi-threaded systems.
• Excellent programming Skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills.
• 5-7 years of prior industry experience in co-op or internship.