Static Timing Analysis Engineer

Key Skills

Python Programming, SQL, Cloud computing

Job Description

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. We are looking for an entry-level Static Timing Analysis (STA) professional who will help with the design, analysis, and implementation of timing fixes on system-on-chip (SOC) designs. Come join our amazing team. College Grads welcome to apply!!

Job Responsibilities:

Responsibilities

• Set up the timing constraints, help to define the overall static timing analysis methodology
• Set up the static timing analysis infrastructure and sign-off convergence flows
• Analyze, debug, and implement fixes for reported timing violations using defined CAD tools/flow
• Work with the global timing team in debugging/resolving any block-level timing issues seen at full chip
• Collaborate with global CAD teams on design flow fixes and feature improvements
• Develop understanding the SOC design requirements and specification
• Develop understanding the computer-aided design (CAD) tools/flow defined for ASICs

Requirements:

Minimum Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 1-3 years of related professional experience
• Master’s degree in Computer Science, Electrical Engineering or related fields with no professional experience
• Knowledge of Static Timing Analysis (STA) and Industry standard Design tools
• Excellent English communication skill in verbal and written
• Able to work effectively with global team and be self-motivated to solve problems and manage deliverables

Preferred Qualifications

• Thorough understanding of Linux/Unix, with experience working on Multi-threaded systems.
• Good programming Skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills
• Experience in transistor and gate-level static timing and noise analysis
• Knowledge of Timing tools and experience in using them in a beginning-to-end project setting in recent semiconductor technology nodes – 5nm/7nm/10nm and 14nm/16nm are preferred but 28nm/32nm acceptable
• 1 year of prior industry experience in co-op or internship