Principal ASIC Design Lead

Key Skills

Apache Hadoop, C Programming, C++, Data science techniques, Java Programming, Machine learning techniques, MapReduce, Python Programming, PyTorch, R Programming, Scala Programming, SQL, TensorFlow

Job Description

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. Marvell provides end-to-end (from RTL to GDS) capabilities using the industry leading Design Automation software and flows to tape out designs to the world’s top fabs in 5nm and smaller geometries. The ASIC Design Lead partners with customers and internal design teams to create optimized designs tailored to customers' needs.

Job Responsibilities:

• Provide technical leadership to a world-wide team of engineers who are implementing customer specific designs from RTL hand-off through tape-out. 
• Lead technical experts across place & route, timing, power, design for test, and packaging domains using design automation tools/flows and scripting languages while employing industry best practices. 
• Work with stakeholders throughout Marvell (e.g., PMO, CAD team, IP team) to meet customer's requirement and specification.
• Align with project management team to meet project schedule and budget. 
• Collaborate and lead global teams with excellent communication skills. 
• Act as a domain expert and provides guidance, feedback and solutions to less-experienced engineers for problems related/unrelated to their projects. 
• Mentor other engineers in their domain expertise area.

Requirements:

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. 
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. 
• Proven track record of leading chip level backend implementation activity and taping out complex SOC chips under tight schedule pressure.
• In-depth understanding of current design technologies used in major foundries.
• Automation minded and an expert familiar with Makefile/Tcl/Perl/Python to improve efficiency and streamline processes.
• Detail oriented and self-motivated team worker with good verbal and written communication skills.
• Must be a power user of P&R tools (Innovus, ICC2, Fusion Compiler).
• Strong knowledge in static timing analysis (PrimeTime, Tempus), EM/IR-Drop/crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction (Quantus, StarRC), formal or physical verification (Formality, Verplex, Calibre, Hercules) and DFT (Tessent, TestMAX, Modus).