Sr Engineer, SoC Design Verification Die-to-Die

Key Skills

Aartificial intelligence, Design, Infrastructure as code

Job Description

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Skilled in SystemVerilog, SV-UVM, and Python with proven verification experience.
• Familiar with AI-assisted coding tools like Copilot, Cursor, or Claude to accelerate DV workflows.
• Comfortable writing detailed test plans, building infrastructure, and debugging complex issues.
• Collaborative engineer who thrives in cross-functional, fast-paced environments.

What We Need

• Develop and maintain D2D tests and supporting verification infrastructure.
• Write, execute, and track test plans for SoC, chiplet, and multi-chip designs.
• Triage, analyze, and debug issues in collaboration with design and architecture teams.
• Leverage modern AI tools to enhance verification productivity and coverage.
• Firmware co-sim with RTL and CPU core debug experience preferred

What You Will Learn

• Gain experience with advanced verification flows for chiplet and multi-die SoCs.
• Work with emerging standards like UCIe and BoW for die-to-die interconnect.
• Explore co-simulation methodologies with frameworks such as Cocotb.
• Build expertise in the intersection of AI tools and state-of-the-art verification practices.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.