Design Implementation Engineer, Intern

Key Skills

Java Programming, Python Programming, C++, C Programming, SQL, Apache Hadoop, Scala Programming, Machine learning techniques, Data science techniques, PyTorch, TensorFlow, MapReduce, R Programming

Job Description

We are looking for Physical Implementation Intern to help us grow our team. This is a great opportunity to become our regular engineer (and does not require the experience). You will be responsible for ASIC Design implementation on our cutting edge ARMv8 based server on chip solutions that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry.

What the Ampere^® Implementation Team wants you to know

Being an Physical Implementation Engineer at Ampere® is interesting, challenging, and will expand your professional breadth. You will learn how the next generation Microprocessor for Cloud Computing developed in Ampere®, powered by Arm64-core and our in-house tooling, to achieve highest performance versus power consumption. And you will learn how a product is developed from R&D to delivery. The experience at Ampere® that you will possess will be valuable for your career path.

What you will do

• Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, function ECO, placement, CTS, route and other sign-off.
• Develop mid-end to back end implementation flows on synthesis, placement, CTS, Route, timing analysis, eco-generation, etc.
• Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners.
• Perform timing closure across all corners to ensure successful tapeout following our aggressive deadlines.
• Generate and implement functional ECO.
• Run Logic Equivalent Check (LEC) from RTL to prelayout/postlayout netlist.

What you will bring

• Third or final year student with GPA of 7.0 points on wards
• Have some basic working knowledge of Semiconductor devices, VLSI designs, ASIC design flow, etc.
• Familiar with UNIX, C, Verilog and Office applications
• Good understanding on SoC, Pcie design is an advantage
• Good debugging, problem solving and presentation skills
• Good communication skills in English and Vietnamese

Education

• BS/MS in Electronic, Computer Engineering, Computer Science or equivalent